Article ID: 000080723 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Is there an issue with the sampling window timing in Stratix III devices when using an ALTLVDS receiver in non-DPA mode?


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    Yes, there is an issue with the sampling window timing in Stratix® III devices when using an ALTLVDS receiver in non-DPA mode for EP3SL200F1517 and EP3SE260F1517 devices. Only ALTLVDS receivers in non-DPA mode driven by a corner PLL are affected by this issue for designs compiled in Quartus® II software version 9.1SP1 and earlier. The LVDS receiver input will sample the input data near the transition region of the bit period instead of the ideal position in the center of the bit period. This increases the risk of input sampling error due to a smaller timing margin.

    ALTLVDS receivers driven by center PLLs are not affected by this issue (PLL_[L,R][2,3]).

    This issue is fixed in Quartus II software version 9.1SP2.  For new designs, the fix in the Quartus II software will improve timing margin on the LVDS links.  For existing designs, the risk to recompile the design is minimal with the condition that you repeat timing analysis upon recompilation.  Any core or I/O logic that is driven by the PLL may have different timing due to the corrected PLL phase shift which optimizes the data sampling position in the ALTLVDS receiver.


    The following patches are available to correct this issue in Quartus II software versions 9.1 and 9.1SP1.  After installing the patch, you need to re-run the fitter, assembler, and TimeQuest to take advantage of the optimized sampling window timing.



    Resolution This is fixed in the Quartus II software version 10.0.

    Related Products

    This article applies to 1 products

    Stratix® III FPGAs