If the state machine is defined so that one or more of the state bits are non-zero in the reset state, then you should explicitly reset the state machine using a reset signal (see below). If the state machine is not explicitly reset in this case, the state machine could power up into an undefined state, and MAX PLUS® II will give the following message:
Info: State machine '<name>' must be reset to guarantee proper operation
To correct this problem, the state machine should be explicitly reset. Examples for AHDL, VHDL, and Verilog HDL design entry formats are shown below.
For AHDL, the reset signal should be declared and asserted.
SUBDESIGN statemachine ( clk, reset, ena, d : INPUT; q : OUTPUT; ) VARIABLE ss: MACHINE WITH STATES (s0=1, s1=0); -- reset state is s0, state register is non-zero BEGIN ss.reset = reset; -- assert this signal to properly reset the state machine <...>
For VHDL, the initial state may be defined by an IF
statement and a reset signal.
ENTITY statemachine IS PORT( clk : IN STD_LOGIC; input : IN STD_LOGIC; reset : IN STD_LOGIC; output : OUT STD_LOGIC); END statemachine; ARCHITECTURE a OF statemachine IS TYPE STATE_TYPE IS (s1, s2); -- reset state is s1 ATTRIBUTE ENUM_ENCODING : STRING; ATTRIBUTE ENUM_ENCODING OF STATE_TYPE : TYPE IS "1 0"; -- state register for s1 is non-zero SIGNAL state : STATE_TYPE; BEGIN PROCESS (clk) BEGIN IF reset = '1' THEN state <= s2; -- causes state machine to power up in state s2 IF (clk'EVENT AND clk = '1') THEN CASE state IS <...>
For Verilog HDL, the initial state must be defined by an IF
statement and a
reset signal, i.e.
module statemachine (clk, in, reset, out); input clk, in, reset; output out; reg out; reg state; parameter s1 = 1, s2 = 0; always @ (state) begin case (state) -- define outputs s1: out = 0; <..> always @ (posedge clk or posedge reset) begin if (reset) state = s1; -- causes state machine to power up in state s1 else case (state) -- define state transitions s1: if (in) state = s2; <...>
For all HDL formats, if you do not define the state machine's initial state to be all zeros, explicitly reset the state machine, since the state machine will power up low.
See the AHDL, VHDL, and Verilog HDL sections of MAX PLUS II Help for complete information on implementing state machines in MAX PLUS II.