Article ID: 000080712 Content Type: Troubleshooting Last Reviewed: 09/08/2014

Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria V GZ and Stratix V devices?

Environment

  • Arria® V GZ FPGA
  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
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Description

When implementing the OBSAI protocol using the Deterministic Latency PHY in Arria V GZ and Stratix V devices, you may fail to achieve rx_syncstatus when IDLE, IDLE_ACK and IDLE_REQ patterns are sent during the link up process. You can achieve synchronization by retriggering rx_patternalign or asserting rx_digitalreset.

This applies to the Deterministic Latency PHY with the following configuration:

  • Data Rate: 6.144 Gbps or 3.072 Gbps
  • PMA-PCS Data Width: 20-bits
Resolution

To work around this issue, follow the steps below:

For Quartus® II software versions before release 14.0:

1. File a Service Request to obtain a software patch

2. Once the patch is installed, add the following assignment to your Quartus II Settings File (.qsf)

set_global_assignment -name VERILOG_MACRO "SV_XCVR_CUSTOM_NATIVE_ASSERT_SYNC_STATUS_IMM=\"assert_sync_status_imm\""

3. Regenerate the Deterministic Latency PHY IP

4. Recompile you design

For Quartus II software versions 14.0 and later:

1. Add the following assignment to your .qsf file

set_global_assignment -name VERILOG_MACRO "SV_XCVR_CUSTOM_NATIVE_ASSERT_SYNC_STATUS_IMM=\"assert_sync_status_imm\""

2. Regenerate the Deterministic Latency PHY IP

3. Recompile your design

If you are implementing both the CPRI and OBSAI protocols in a single device, open a Service Request for further support.

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