Article ID: 000078002 Content Type: Troubleshooting Last Reviewed: 09/08/2014

Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria V GX/GT devices?

Environment

  • Arria® V GX FPGA
  • Arria® V GT FPGA
  • Arria® V FPGAs and SoC FPGAs
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When implementing the OBSAI protocol using the Deterministic Latency PHY in Arria® V GX/GT devices, you may fail to achieve rx_syncstatus when IDLE, IDLE_ACK and IDLE_REQ patterns are sent during the link up process. You can achieve synchronization by retriggering rx_patternalign or asserting rx_digitalreset.

This applies to the Deterministic Latency PHY with the following configuration.

  • Data Rate: 6.144 Gbps
  • PMA-PCS Data Width: 20-bits

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.