Article ID: 000080674 Content Type: Troubleshooting Last Reviewed: 04/11/2019

Why does the reset_status signal toggles after pin_perst signal is released in the Stratix® V Avalon® ST Interface for PCIe* IP?

Environment

    Quartus® II Subscription Edition
    Intel® Quartus® Prime Standard Edition
    Stratix® V Hard IP for PCI Express Intel® FPGA IP
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Critical Issue

Description

When using the Stratix® V Avalon®-ST Interface for PCIe* IP, you may observe the reset_status signal toggling after pin_perst is released and before ltssmstate signal reaches Polling.Active (0x2). You can safely ignore this behavior and sample reset_status signal until the ltssmstate signal is greater than Polling.Active (0x2).

Resolution

This information is scheduled to be added in a future release of the Stratix® V Avalon® ST Interface for PCIe* Solution User Guide.

Related Products

This article applies to 1 products

Stratix® V FPGAs

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