Article ID: 000080663 Content Type: Product Information & Documentation Last Reviewed: 07/03/2019

How to disable EDID pass through in DisplayPort Intel® Arria® 10 FPGA IP Design Example?

Environment

  • Intel® Quartus® Prime Pro Edition
  • DisplayPort Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Extended Display Identification Data (EDID) contains sink device (e.g. monitor) information such as the supported video resolution and timing standard.

    When Enable GPU Control option is turned on in the DisplayPort IP core parameter editor of the DisplayPort Intel® Arria® 10 FPGA IP Design Example with Sink-Source parallel loopback, the NIOS® II processor will enable the 'EDID pass through' to receive the EDID from sink device (e.g. monitor) and pass it to source device (e.g. Graphic Processor Unit).

    In applications that instantiate DisplayPort sink only, there is no DisplayPort source in the FPGA to pass the EDID from the monitor to the GPU (Graphic Processor Unit). Therefore, the EDID pass through must be disabled so that the default EDID (altera_4k_edid) in main.c in the software folder is read by the GPU.

    Resolution

    To disable EDID pass through, open config.h file in the software folder and change the DP_SUPPORT_EDID_PASSTHRU parameter to 0 and run the build_sw.sh script to rebuild the NIOS® II software. Download the NIOS II® software image (dp_demo.elf) located in the software/dp_demo folder into the FPGA.

     

    // EDID PassThru from Sink to Source

    #define DP_SUPPORT_EDID_PASSTHRU 0   // Set to 1 to enable EDID passthru from Sink to Source.

                                                                                     // Else DP Sink will use default EDID.

                                                                                     // Only Support EDID passthru when both Tx and Rx is supported

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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