Description
Due to problem in the Quartus® Prime software Standard edition version 15.1, you may see this warning message in the TimeQuest Timing Analyzer when using the Altera Dual Configuration IP. This problem is seen in design targetting MAX® 10 devices.
Resolution
To work around this problem, apply the following constraint in the sdc file
create_generated_clock -name {ru_clk} -source [get_ports {clk}] -divide_by 2 -master_clock {clk} [get_registers {*ru_clk}]
