Article ID: 000080607 Content Type: Troubleshooting Last Reviewed: 04/13/2017

Why is there an unconstrained clock, altera_dual_boot: dual_boot_0|alt_dual_boot_avmm: alt_dual_boot_avmm_comp|alt_dual_boot: alt_dual_boot|ru_clk?

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to problem in the Quartus® Prime software Standard edition version 15.1, you may see this warning message in the TimeQuest Timing Analyzer when using the Altera Dual Configuration IP. This problem is seen in design targetting MAX® 10 devices.

    Resolution

    To work around this problem, apply the following constraint in the sdc file

                 create_generated_clock -name {ru_clk} -source [get_ports {clk}] -divide_by 2 -master_clock {clk} [get_registers {*ru_clk}]

     

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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