Article ID: 000080579 Content Type: Troubleshooting Last Reviewed: 05/20/2013

Some CPRI IP Core Variations Configured with the Advanced 1 Mapping Mode Might Not Achieve Timing Closure

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If your CPRI IP core variation is configured with Mapping mode set to Advanced 1, and the target device family and CPRI line rate are set to any of the following combinations, your CPRI IP core may fail to achieve timing closure.

    Timing closure failure has been observed in the following combinations of target device family and CPRI line rate:

    • Arria V device at CPRI line rate 6.144 Gbps
    • Stratix V device at CPRI line rate 9.8304 Gbps
    Resolution

    This issue has no workaround.

    This issue is fixed in version 12.1 of the CPRI MegaCore function.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs