Article ID: 000080547 Content Type: Troubleshooting Last Reviewed: 03/15/2013

No 28nm Device Support for 10G Soft-XAUI Design Example

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The 10G soft-XAUI design for the Stratix V PCI Express (PCIe) development kit is unable to complete the fitter process when the pin assignments at the high-speed mezzanine card (HSMC) Port A are using the transceiver channels 0, 2, 3, and 4.

The 10G XAUI hardware design cannot be tested for the Stratix V SI development kit because the design is unable to interface with the external tester.

The 10G XAUI design is unable to meet the timing analysis for the Cyclone V PCIe development kit in the Quartus software.

This issue affects the 10G Ethernet 12.1 designs in the Cyclone V and Stratix V 28nm devices.

Resolution

There is no workaround for this issue.

This issue will be fixed in a future ACDS release.

Related Products

This article applies to 2 products

Cyclone® V FPGAs and SoC FPGAs
Stratix® V FPGAs

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