Why does my altera_syncram output an X instead of valid data in simulation?

Due to a problem in the Intel® Quartus® Prime Pro Edition software, you may see an output of "X" instead of valid data during simulation. This problem occurs when the following conditions are true:

• The RAM is configured with different read and write clocks
• The RAM is configured in dual port mode
• The RAM is configured with read_during_write_mixed_ports set to dont_care
• The write address (address_a) and read address (address_b) are triggered at the current clock cycle
• The write enable signal (wren_a) was de-asserting in the previous clock cycle (during positive clock edge)

To work around this problem, do not trigger any control signal on the positive clock edge.

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro Edition software.