Article ID: 000080423 Content Type: Troubleshooting Last Reviewed: 06/10/2019

Why does the CPRI v6.0 Intel® FPGA IP generate multiple start-of-packet words on the GMII RX Output?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® CPRI
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem with the CPRI v6.0 Intel® FPGA IP core in the Intel® Quartus® Prime software v17.1, you may observe multiple initial start-of-packet on the GMII RX output if there are idle cycles in the gmii_rxdv within a packet. 

Resolution

No workaround for this problem exists.

This problem has been fixed in Intel® Quartus® Prime Edition software version 19.1.

Related Products

This article applies to 5 products

Cyclone® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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