Why is an unconstrained clock error reported when using the Error Message Register Unloader Intel® FPGA IP on the Intel® Arria® 10 FPGA?

An unconstrained clock is reported as shown below when using the Error Message Register Unloader Intel® FPGA IP on the Intel® Arria® 10 FPGA:

emr_unloader_component|current_state.STATE_CLOCKHIGH

To work around this problem, generate timing constraints including the command "create_generated_clock" in the SDC file. For example:

create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_nets {* |alt_fault_injection_component|alt_fi_inst|twentynm_oscillator}] [get_keepers {* |emr_unloader_component|current_state.STATE_CLOCKHIGH}]