Article ID: 000080395 Content Type: Troubleshooting Last Reviewed: 11/22/2023

Why do I get a compilation error when my design partition contains an Intel® Arria®10 Transceiver?

Environment

  • Intel® Quartus® Prime Standard Edition
  • Transceiver ATX PLL Intel® Arria® 10 Cyclone® 10 FPGA IP
  • Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
  • fPLL Intel® Arria® 10 Cyclone® 10 FPGA IP
  • Transceiver CMU PLL Intel® Arria® 10 Cyclone® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Intel® Quartus® Prime Standard Edition Software, you may see an error when your design partition contains an Intel® Arria® 10 Transceiver PHY and/or Transceiver PLL.

     

    Resolution

    The Quartus® Prime Standard Edition Software does not support partitions for Arria® 10 Transceiver PHY and/or Transceiver PLL. 

    Exclude the Arria® 10 Transceiver PHY or Transceiver PLL from the design block before creating the partition.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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