Article ID: 000080369 Content Type: Troubleshooting Last Reviewed: 07/01/2019

Why does the register csr_sysref_singledet not get cleared after SYSREF detection in the JESD204C IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • JESD204B Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2, in a single SYSREF generation subclass 1 system, the JESD204C IP will not enter the user phase due to it waiting for csr_sysref_singledet deassertion. 

    Resolution

    To work around this do the folowing :

    1. After SYSREF pulse generation, assert csr_cgs_bypass_sysref to enter user phase manually.

     2. Send another SYSREF pulse 

    This problem is scheduled to be fixed in future release of the Intel® Quartus®  Prime Pro Edition software. 

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 TX FPGA

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