Article ID: 000080366 Content Type: Troubleshooting Last Reviewed: 03/16/2021

Why does the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core fail to simulate using Cadence* NCSim and Xcelium when the RS-FEC is enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core in RS-FEC mode, simulation will fail in both Cadence* NCSim and Xcelium.

    An Error similar to the one shown below will be seen:

    ncsim: *F,NOSNAP: Snapshot 'basic_avl_tb_top' does not exist in the libraries.

    Resolution

    To work around this problem, please use Synopsys* VCSMX or disable the RS-FEC.

    This problem is not scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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