Article ID: 000080298 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I receive a warning related to the width of the "rx_recovered_clk" of the XAUI PHY IP?


  • Quartus® II Subscription Edition

    There is a known issue with the XAUI PHY IP in which the port width of the "rx_recovered_clk" signal in the generated HDL from the MegaWizard™ is the incorrect width.  The width is 3-bits wide when it should be 4.

    This issue was introduced in Quartus® II v11.0 and v11.0sp1, but has been fixed as of v11.1.  Affected devices include all Stratix® IV, Arria® II, Cyclone® IV, and HardCopy® IV variants that include transceivers.


    A workaround for Quartus II v11.0 is to manually change the width to be 4 bits.  This workaround is also valid for Qaurtus II v11.0sp1.  However, a patch exists that can be applied to Quartus II v11.0sp1.  This patch can be downloaded using the following links:

    Quartus II software version 11.0SP1 patch 1.32 for Windows

    Quartus II software version 11.0SP1 patch 1.32 for Linux

    Quartus II software version 11.0SP1 ReadMe for patch 1.32

    Related Products

    This article applies to 8 products

    Stratix® IV FPGAs
    Arria® II FPGAs
    Cyclone® IV FPGAs
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Arria® II GX FPGA
    Arria® II GZ FPGA
    HardCopy™ IV GX ASIC Devices