Why are my Stratix IV PLL's merged together even if they do not share common inputs?

Due to a problem in the Quartus® II software version 10.1 SP1 and later, Stratix® IV PLLs which share a common phaseclock_select port may incorrectly be merged together even if the remaining ports of the two PLLs are not common.

This problem may lead to functional problems in gate-level simulation and hardware.

To work around this issue, turn off the Auto Merge PLLs Fitter Setting that prevents the Quartus II software from merging the PLLs.

This problem is scheduled to be resolved in a future release of the Quartus II software.