Article ID: 000080127 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is my Stratix read DQS signal is stuck at an incorrect phase shift?


Description When using the DQS signals in Stratix devices, you need to make sure that the DLL reference clock to the FPGA is always valid after configuration. This means that the DLL reference clock needs to meet the VIH and VIL specification of the IO standard. If the DLL reference clock does not meet the specified voltage levels, the DLL initialization phase may get corrupted resulting in an incorrect phase shift value. Even though the DLL is self-calibrating, if the counter base values get corrupted during initialization, the offset for the phase shift will be incorrect and cannot be updated unless you power-cycle the device.

When debugging this problem, first check the termination on the DLL reference clock. A pull-up to VTT could permit your DLL reference clock signal to go to an indeterminate state when there is nothing driving the line.

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Stratix® FPGAs