Article ID: 000080103 Content Type: Troubleshooting Last Reviewed: 07/27/2015

Why do I see timing violations in the Stratix V and Arria V GZ device Reconfiguration Controller IP when the Bit Error Rate block is enabled?

Environment

  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Arria® V GZ FPGA
  • Stratix® V GS FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to the "set_max_skew" constraint contained in the reconfiguration controller's alt_xcvr_reconfig.sdc file, you might see timing violations in the Stratix® V and Arria® V GZ device Reconfiguration Controller IP when the Bit Error Rate Block is enabled. 
    Resolution To help close timing, the "set_max_skew" constraint can be removed from the alt_xcvr_reconfig.sdc file. This will reduce congestion and routing effort due to the Bit Error Rate accumulators.

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