Article ID: 000080079 Content Type: Troubleshooting Last Reviewed: 12/03/2014

Why are the Arria 10 DDR4 Mode Register 4 (MR4) write/read preamble bits set incorrectly?

Environment

    Quartus® II Subscription Edition
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Description There is a known issue in the Quartus® II software version 13.1 Arria 10 Edition where the DDR4 MR4 write/read preamble bits are set incorrectly.
Resolution The issue is fixed in the Quartus II software version 14.0 Arria 10 Edition.

Related Products

This article applies to 3 products

Intel® Arria® 10 GX FPGA
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 SX SoC FPGA

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