Article ID: 000079963 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does formal verification software show mismatches when the golden VQM netlist contains an lpm_mult megafunction?


  • Verification
  • DSP

    Mismatches occur when the golden netlist contains an lpm_mult megafunction implemented in logic with the lpm_pipeline parameter is greater than 0.

    The Quartus® II software implements lpm_mult megafunctions in logic instead of a DSP block in the following situations:

    • The design targets a device without DSP blocks, such as a Cyclone device.
    • The number of lpm_mult megafunctions in the golden design is greater than the number of available DSP blocks in the target device.
    • You specify that the lpm_mult megafunction be implemented in logic.

    To work around this problem:
    If you instantiate the lpm_mult megafunction in your RTL code, apply the black box property to the module that instantiates the lpm_mult megafunction. If your synthesis tool infers the lpm_mult megafunction, create a wrapper file around the multiplier and apply the black box property to the wrapper module.

    For more information on formal verification, refer to the Formal Verification section in volume 3 of the Quartus II Handbook.