Article ID: 000079921 Content Type: Troubleshooting Last Reviewed: 11/23/2011

Write Timing Violation at 550MHz for QDR II and QDR II SRAM Controller with UniPHY

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

Designs targeting Stratix V devices at 550MHz may produce write timing violations.

Resolution

There is no workaround for this issue.

Related Products

This article applies to 1 products

Stratix® V FPGAs

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