Article ID: 000079845 Content Type: Troubleshooting Last Reviewed: 11/24/2011

Fitter Error When Compiling DDR2 Designs Below 240MHz in DDR2 and DDR3 SDRAM Controller with UniPHY

Environment

    Quartus® II Subscription Edition
    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

For DDR2 designs operating at frequencies of 240MHz or less, the Fitter might display the error message: Can’t place Top/Bottom or Left/Right PLL.

Resolution

The workaround for this issue is to turn on the Remove Duplicate Registers synthesis option.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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