Article ID: 000079827 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Why do I see incorrect initialization of my Arria® V M10K memory blocks?

Environment

    Quartus® II Software
    Arria® V Transceiver Native PHY Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software version 13.0sp1 and earlier, you may find the initial content of Arria® V M10K memory blocks to be incorrect in hardware.

The problem is specific to cases where two single-port RAM blocks are packed into a single M10K resource where both RAM blocks have constant (VCC or GND) read or write enables.

Resolution

Connect the read and write enable signals to dynamic signals so they are not tied to VCC or GND.

This issue has already been fixed in the Quartus® II software version 15.0.

Related Products

This article applies to 4 products

Arria® V GT FPGA
Arria® V GX FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.