Article ID: 000079784 Content Type: Product Information & Documentation Last Reviewed: 06/30/2014

How can I resolve Quartus II software "HSSI_PMA_AUX" associated fitter errors when compiling with Stratix V, Arria V, and Cyclone V transceiver devices?

Environment

  • Cyclone® V SX SoC FPGA
  • Cyclone® V GT FPGA
  • Stratix® V GX FPGA
  • Cyclone® V GX FPGA
  • Stratix® V GT FPGA
  • Stratix® V GS FPGA
  • Arria® V GZ FPGA
  • Arria® V SX SoC FPGA
  • Cyclone® V ST SoC FPGA
  • Arria® V ST SoC FPGA
  • Arria® V GX FPGA
  • Arria® V GT FPGA
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Description

Quartus® II software "HSSI_PMA_AUX" associated fitter errors when compiling with Stratix® V, Arria® V, and Cyclone® V transceiver devices are typically associated with the transceiver reconfiguration controller IP.

If you see Quartus II software "HSSI_PMA_AUX" fitter errors when compiling with Stratix V, Arria V, and Cyclone V transceiver devices you should double check the following key areas in your design.

    • Check that you have connected up your reconfig_to_xcvr and reconfig_from_xcvr busses between the transceiver and reconfiguration controller correctly.
    • Ensure that all transceiver IP in your design are connected to a reconfiguration controller. If one transceiver is connected to a reconfiguration controller, all transceivers must be.
    • Ensure that you do not exceed more than one reconfiguration controller IP instance per transceiver half-block (bottom-three, or top-three channels in a transceiver bank). You can refer to the "Transceiver Reconfiguration Controller to PHY IP Connectivity" chapter of the transceiver PHY IP Userguide for further information.
    • If you have more than one reconfiguration controller IP in your design that share a common Calibration Block, ensure that they have a common mgmt_clk_clk clock source. You can refer to the "Calibration Block Boundary" section of the Transceiver Architecture in Stratix V Devices chapter of the Stratix V GX handbook for details of Calibration Block boundaries.
    • If you are using PCI Express CvP, you should also ensure that you adhere to the following advice on reconfiguration controller mgmt_clk_clk clock source requirements.

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