Article ID: 000079768 Content Type: Troubleshooting Last Reviewed: 02/20/2014

SDRAM ECC Disabled in Preloader

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

Qsys cannot generate a DDR interface in the HPS component with ECC enabled. If you try to specify such an interface, the result is an interface with no ECC. Depending on the interface width specified, the resulting interface width is as follows:

Specified widthResulting width
2416
4032
Resolution

Upgrade to the Altera Complete Design Suite v13.0 SP1 or later.

Related Products

This article applies to 1 products

Cyclone® V FPGAs and SoC FPGAs

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