Article ID: 000079758 Content Type: Error Messages Last Reviewed: 01/01/2015

Error: <system name>.hps_0: "HPS-to-FPGA user <0,1,2> clock frequency" (S2FCLK_USER<0,1,2>CLK_FREQ) < frequency > is out of range: < osc1 frequency > - 100.0

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software version 14.0,  Qsys incorrectly restricts the minimum frequency of HPS User Clocks to the frequency of the external reference clock (OSC1/2).


 

Resolution

To work around this problem manually edit the PLL settings for the user clocks in the <BSP>/generated/pll_config.h file before running make to build the Software pre loader.

Please see the Preloader Clocking Customization Page on www.Rocketboards.org for information on manually editing pll_config.h

This problem has been resolved for the next release of the Quartus II Software

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA

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