Article ID: 000079732 Content Type: Troubleshooting Last Reviewed: 04/21/2023

Why does my Altera PLL megafunction, with dynamic phase shift ports enabled, fail to lock in simulation?

Environment

    Quartus® II Subscription Edition
    Avalon ALTPLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Altera® PLL mega function, with dynamic phase shift ports enabled, may fail to lock if the scanclk input is not toggling when the refclk input starts toggling in simulation.  In this case, the locked output signal and the output clocks will be stuck low. 

You may also receive the following message if you are using ModelSim:
"# ** Error: (vsim-8630) nofile(-1): Infinity results from division operation."

This is due to a problem in the simulation model and does not represent the actual behavior of the device where the scanclk input may be free running.

 

 

Resolution

Ensure that the scanclk input is set to logic 1 when not toggling.

Related Products

This article applies to 14 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
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Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V E FPGA

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