Article ID: 000079688 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

These assignments which are applied to UniPHY based IP's reset and clock signals are correct and no changes are required by the user.

The assignments are shown with Status “?”. This is due to a display issue in Assignments editor and is planned to be fixed in a future version of the Quartus® II software.

Related Products

This article applies to 12 products

Stratix® III FPGAs
Stratix® IV FPGAs
Stratix® V FPGAs
Arria® II GX FPGA
Arria® II GZ FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® V GS FPGA
Stratix® V E FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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