Article ID: 000079654 Content Type: Troubleshooting Last Reviewed: 03/27/2023

Why does a delay sometimes occur when accessing DDR3 memory?


  • Quartus® II Subscription Edition

    In the Quartus® II software version 12.1, when the UniPHY DDR3 IP configuration is for a single rank interface and meets these requirements, DQS tracking is enabled:

    Intel® Stratix® V, Arria® V GZ.   Memory clock frequency >= 750MHz

    Arria® V (GX, GT, SX, ST): Memory clock frequency  >= 534 MHz.  For a -5 speed grade device when the memory clock frequency >= 450MHz.  


    During DQS tracking, the user's application will see a delay in obtaining DDR3 memory access.

    There are two different types of delays :

    1) DQS tracking samples occur after every memory refresh cycle and are memory reads. For a quarter rate interface, this typically takes around 800ns.
    2) DQS tracking updates: Once sufficient DQS tracking samples have been accumulated, an update to the DDR3 data path I/O delay settings occurs, which results in a longer delay. DQS tracking updates take at least 4us and increase with the number of DQS groups in the interface.

    If these delays do not affect your application, you don't need to change anything.
    If these delays affect your application, you can use the workaround below.


    1) Edit the top-level DDR3 IP file in the // Retrieval info: parameters section and set these two parameters as shown below:-

    generic name="FORCE_DQS_TRACKING" value="DISABLED"
    generic name="ENABLE_EXTRA_REPORTING" value="true"  (Only change this parameter if the IP is generated in Quartus® II 12.1.  If generated in the Quartus® II software version 12.1SP1 or later, the postamble timing is reported by default)

    2) Regenerate the IP.

    3) Compile the project.

    4) Observe Timequest Report DDR. 

    There are additional timing margins shown, including postamble. DQS tracking only affects postamble timing.

    If postamble timing has positive margins in all of the Timequest timing model cases (slow and fast at the temperature limits), the generated IP code with DQS tracking disabled can be used in your project.

    If any other TimeQuest Report DDR timing margins show a negative margin, this is a different issue to resolve.

    If postamble timing shows a negative margin, please get in touch with Altera.

    Related Products

    This article applies to 9 products

    Arria® V GT FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Stratix® V GX FPGA
    Arria® V GZ FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V E FPGA
    Arria® V GX FPGA