Why does my Arria V or Cyclone V PCI Express core fail to downtrain to a x2 or x1 configuration?

The Arria® V and Cyclone® V Hard IP for PCI Express® IP Cores do not downtrain to x1 or x2 from a x4 or x8 configurations.

The workaround is to correct the Verilog HDL code in altpcie_av_hip_128_bit_atom.v that sets the number of lanes. This correction should be made to the file located in the Quartus® II installation directory <quartus12.0_install_path>\ip\altera\altera_pcie\altera_pcie_av_hip_ast.  Be sure that any copy of this file located in the project folder due to the MegaWizard™ or Qsys tools are deleted and the PCIe variant regenerated.

Replace this incorrect code:

wire rxstatus_err;

assign rxstatus_err = (pld8grxstatus0[2] | pld8grxstatus1[2] | pld8grxstatus2[2] | pld8grxstatus3[2] | pld8grxstatus4[2] | pld8grxstatus5[2] | pld8grxstatus6[2] | pld8grxstatus7[2]);

assign rxstatus_err = pld8grxstatus0[2];

With this corrected version:

wire rxstatus_err rxstatus_err_x1, rxstatus_err_x4, rxstatus_err_x8;

assign rxstatus_err_x8 = (pld8grxstatus0[2] | pld8grxstatus1[2] | pld8grxstatus2[2] | pld8grxstatus3[2] | pld8grxstatus4[2] | pld8grxstatus5[2] | pld8grxstatus6[2] | pld8grxstatus7[2]);

assign rxstatus_err_x4 = (pld8grxstatus0[2] | pld8grxstatus1[2] | pld8grxstatus2[2] | pld8grxstatus3[2] );

assign rxstatus_err_x1 = pld8grxstatus0[2] ;

assign rxstatus_err = (lane_act==4\'b1000)?rxstatus_err_x8:(lane_act==4\'b0100)?rxstatus_err_x4:rxstatus_err_x1;

This issue will be fixed in future version of the Arria V and Cyclone V Hard IP for PCI Express IP Cores.