Article ID: 000079550 Content Type: Troubleshooting Last Reviewed: 08/29/2012

Why are my wrfull and rdempty signals in my Dual-Clock first-in first-out (FIFO) megafunction asserted at the same time?


Description When using aclr in the Altera® Dual-Clock FIFO megafunction, you need to ensure that the falling edge of aclr never occurs on the rising edge of the write clock. When that condition occurs there is the possibility that one of the counters (read or write), transitions while the other one does not. This causes the read side and the write side to disagree on how many words there are in the FIFO. For example, one counter will see the aclr longer than the other if there is skew on the aclr line.

You can delay aclr about half a cycle before going to the FIFO by adding a D flipflop (DFF) where the inverted aclr is connected to the preset port of the DFF and the inverted wrclk is connected to the DFF clock, with the D port of the DFF connected to ground. You can then use the output of the DFF as the aclr of your FIFO; this guarantees that the falling edge of aclr will never occur on the rising edge of the write clock. An alternative of this workaround is to have wrreq low while aclr is active to guarantee that neither counter will transition.

You do not have to worry about the read side if you turn underflow checking on. The FIFO is emptied when aclr is asserted, which in turn ignores all read requests. This is similar to holding rdreq low.

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Stratix® FPGAs