Article ID: 000079463 Content Type: Troubleshooting Last Reviewed: 09/25/2014

Low Latency 40-100GbE IP Core Timing Issues in 14.0 Arria 10 Edition Release

Environment

    Quartus® II Subscription Edition
    Ethernet
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Critical Issue

Description

When you compile the Low Latency 40-100GbE IP core released with the Quartus II software v14.0 Arria 10 Edition, you might encounter the following timing issues:

  • CAUI-4 LL 40-100GbE IP core variations might flag pulse width violations
  • LL 100GbE IP core variations might have setup violations
  • All LL 40-100GbE IP core variations might have hold violations
Resolution

This issue has no workaround.

This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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