Critical Issue
Description
The Synopsys Design Constraints (SDC) listed for the PHY IP Core for PCI Express (PIPE) in the Altera Transceiver PHY IP Core User Guide are incorrect. The correct constraints are listed below.
#analyzing at 250 MHz
create_generated_clock -name clk_g3 -source [get_ports
{pll_refclk}]
divide_by 2 -multiply_by 5 -duty_cycle 50 -phase 0 -offset
0[get_nets
{*pipe_nr_inst|transceiver_core|inst_sv_xcvr_native|inst_sv_pcs|ch[*].
inst_sv_pcs_ch|inst_sv_hssi_tx_pld_pcs_interface|pld8gtxclkout}]
-add
#analyzing at 62.5MHz
create_generated_clock -name clk_g1 -source [get_ports
{pll_refclk}]
-divide_by 8 -multiply_by 5 -duty_cycle 50 -phase 0 -offset
0
[get_nets
{*pipe_nr_inst|transceiver_core|inst_sv_xcvr_native|inst_sv_pcs|ch[*].
inst_sv_pcs_ch|inst_sv_hssi_tx_pld_pcs_interface|pld8gtxclkout}]
-add
#creating false paths between these clock groups
set_clock_groups -asynchronous -group [get_clocks clk_g3]
set_clock_groups -asynchronous -group [get_clocks clk_g1]
set_clock_groups -asynchronous -group [get_clocks
*pipe_nr_inst|transceiver_core|inst_sv_xcvr_native|inst_sv_pcs|ch[*].
inst_sv_pcs_ch|inst_sv_hssi_8g_tx_pcs|wys|clkout]
Resolution
These timing constraints for the PHY IP Core for PCI Express are included in version 13.0 SP1 of the Altera Transceiver PHY IP Core User Guide.