Article ID: 000079435 Content Type: Troubleshooting Last Reviewed: 07/04/2016

DisplayPort IP Core Transmits Unexpected Last Pixel Data At the End of Every Video Line

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The DisplayPort TX core may transmit video with unexpected last pixel data at every end of video line for certain combination of resolution and color depth. This issue may occur when the total symbols (TS) required to transmit active pixel data per line per lane is not in multiple of SYMBOLS_PER_CLOCK (2 or 4).

    This issue is caused by the flaw in the packetizer array indexing.

    The total symbols required per line per lane (TS) across color depths can be calculated as:

    16 bpp: TS = (active pixels per line x (4 x 1) / 2) / lane count

    18 bpp: TS = (active pixels per line x (4 x 9) / 16) / lane count

    20 bpp: TS = (active pixels per line x (4 x 5) / 8) / lane count

    24 bpp: TS = (active pixels per line x (4 x 3) / 4) / lane count

    30 bpp: TS = (active pixels per line x (4 x 15) / 16) / lane count

    32 bpp: TS = (active pixels per line x (4 x 2) / 2) / lane count

    36 bpp: TS = (active pixels per line x (4 x 9) / 8) / lane count

    48 bpp: TS = (active pixels per line x (4 x 3) / 3) / lane count

    For a resolution example of 1,368 active pixels per line, 30 bpp and lane count of 2, the total symbols required per line per lane is

    1,368 x (4 x 15) / 16 / 2 = 2565

    The value of 2,565 is not a multiple of 2 or 4. This means you may observe unexpected last pixel data at the end of every video line.

    Resolution

    There is no workaround for this issue.

    This issue is fixed in version 16.0 of the DisplayPort IP core.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices