Article ID: 000079344 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do the M9K or M144K memory blocks in Stratix IV devices fail to have new data written even though the write related control signals are functioning correctly?



If the clock signal does not meet the minimum pulse width specification (clock high time and clock low time) at all times when performing a write operation (wren=1), new data may not be written correctly into the memory block in Stratix® IV devices. Clock signals that violate this specification may cause unexpected memory behavior in the following modes:


  • M144K
    • True-Dual-Port, Read-Before-Write
    • Simple-Dual-Port, Read-Before-Write
  • M9K
    • True-Dual-Port, Read-Before-Write

Read-Before-Write mode is selected if any of the following conditions is met:

  •  Same port read-during-write parameter is set to “NEW_DATA_WITH_NBE_READ” OR
  •  Same port read-during-write parameter is set to “OLD_DATA” OR
  •  Mixed port read-during-write parameter is set to “OLD_DATA”

If the clock signal integrity cannot be guaranteed on your application, you may perform one of the following options: 

  • Disable the write operation (wren=0) when the clock is unstable (e.g during power up or configuration of external clock source)
  • Use the on-chip PLL as the input clock source to the memory block
  • Perform a chip-wide global reset by asserting DEV_CLRn for more than 500µs when the clock becomes stable
  • Use Fast Write mode. This mode is selected when the same port read-during-write parameter is set to “NEW_DATA_NO_NBE_READ” AND the mixed port read-during-write parameter is set to "DONT_CARE”

Related Products

This article applies to 3 products

Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA