Are there any recommendations when using more than one ATX PLL that run at the same Voltage Controlled Oscillator (VCO) frequency in Arria V GZ and Stratix V transceiver devices?

Yes, there are placement recommendations when using more than one ATX PLL that run at the same VCO frequency in Arria® V GZ and Stratix® V transceiver devices.

For optimal ATX PLL performance you should ensure that no two ATX PLLs that run at the same VCO frequency are adjacent to each other. This recommendation applies to adjacent ATX PLLs that reside in the same transceiver bank and also adjacent ATX PLLs in neighboring transceiver banks.

An example Quartus® II Software Settings File (.qsf) assignment for hand placing ATX PLLs is as follows.

set_location_assignment LCPLL_X0_Y33_N57 -to "test_phy:phy|altera_xcvr_native_sv:test_phy_inst|sv_xcvr_plls:gen_native_inst.xcvr_native_insts[0].gen_bonded_group_plls.gen_tx_plls.tx_plls|pll[0].pll.atx_pll.tx_pll"

You can determine the ATX PLL coordinates by inspecting the Quartus II software Floorplanner.