The Handbook for the respective device will have the information on the maximum number of DQ/DQS groups allowed per side. The Handbook will also tell you the maximum number of data pins per DQ/DQS group for the particular type of memory technology you are using. This data allows you to determine the maximum size of an interface that you can have on a single side of the FPGA.
If you want to implement a hybrid interface where you have data pins on multiple sides of the FPGA, you determine the pins that the DLL can connect to and change your calculations accordingly.
For example, with Stratix® IV, the handbook chapter External Memory Interfaces in Stratix IV Devices (PDF), Table 7-7 on page 36 states that DLL1 can connect to all the banks that are adjacent to it (ie. Banks 1A, 1B, 1C ,2A, 2B, 2C ,7A, 7B, 7C and ,8A, 8B, and 8C).
The External Memory PHY Interface Megafunction User Guide (Altmemphy) (PDF) also gives you the information on the maximum supported memory interface data width for all the memory controllers (the maximum data width is 288 bits).