Article ID: 000079090 Content Type: Troubleshooting Last Reviewed: 08/27/2012

Why do I see large routing wire delay added to my input and output paths resulting in timing violations?

Environment

    Quartus® II Subscription Edition
    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to an problem in the Quartus® II software versions 12.0 and 12.0 SP1, PLL compensation may be modeled incorrectly in the Fitter. This may result in large routing wire delay added to paths that cross clock domains such as input and output paths. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices.
Resolution

This problem has been fixed in the Quartus II software version 12.0 SP2. To work around this problem, upgrade to the Quartus II software version 12.0 SP2.

Related Products

This article applies to 14 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

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