If you attempt to compile a design that targets a Stratix V device, compilation might fail with the following error:
Error: Unable to generate the EDA simulation netlist
files because the Quartus II software does not currently support
gate-level simulation for the Stratix V devices.
Before you start a compilation, turn off the netlist writer by performing the following steps:
- On the Assignments menu, click Settings.
- In the Category list, select Simulation under EDA Tool Settings.
- In the Tool name box, select <None>.
To perform a nativelink RTL simulation, after compilation is completed, select your EDA tool in the Tool name box of the EDA Settings dialog box..