Article ID: 000078896 Content Type: Error Messages Last Reviewed: 07/17/2014

Error: {variation_name}_p0_pin_map.tcl: Failed to find PLL reference clock

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see the above error when the PLL reference clock input to the UniPHY-based memory controller is fed from another PLL. While it is not recommended to cascade PLLs, it is allowed and the design should compile with warnings but no errors.

    The cause of the above error is that the number of hierarchical levels for the reference clock has exceeded the value in the <variation_name>_p0_get_input_clk_id procedure in the <variation_name>_p0_pin_map.tcl file.

    Resolution

    Perform the following steps to fix the error:

    • Open the <variation_name>_p0_pin_map.tcl file
    • Search for the string results_array 9
    • Change the value from 9 to a larger value, e.g. 20
    • Save the <variation_name>_p0_pin_map.tcl file
    • Re-compile the design and you should not see the above error

    Related Products

    This article applies to 1 products

    Stratix® V GS FPGA

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