Article ID: 000078771 Content Type: Troubleshooting Last Reviewed: 03/21/2016

Why is the UniPHY based memory controller design not meeting timing?



You may notice large timing violations in the Report DDR timing report for your UniPHY memory controller design if you use the derive_pll_clocks directive in the SDC file for your design. If the SDC file containing the derive_pll_clocks constraint is called before the UniPHY SDC file is called in the Quartus® II software, TimeQuest will create clocks for the UniPHY PLL output clocks. These created clocks will have different names compared to the clocks created by the UniPHY SDC file hence TimeQuest will not be able to properly analyze the UniPHY based IP because of the conflicting clock names.


The workaround is to make sure that the UniPHY QIP file is listed before the design SDC file for the project. In Quartus, open the "Project > Add/Remove Files in Project..." window, select the UniPHY QIP file, and click the "Up" button until the QIP file is at the top of the list or you can also make the changes in QSF file to call the UniPHY IP QIP file first.

An alternate workaround is to remove the derive_pll_clocks directives in your SDC files.

Note that it is not recommended to remove the derive_pll_clocks directive from Altera® IP cores.

Related Products

This article applies to 8 products

Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA



All postings and use of the content on this site are subject to Terms of Use.