Some configurations of transceiver TX channels used in Deterministic Latency mode will result in incorrect timing analysis in the Quartus® II software. In these specific cases the timing analyzer ignores clock paths from the pll_inclk, through the TX PLL, and preceding the TX PCS block resulting in an incorrect timing analysis on the affected paths. These affected paths may appear to have proper timing closure, which masks potential timing violations due to the incorrect timing analysis.
The following device families and configurations are affected:
- Stratix® IV GX, Stratix IV GT, Arria® II GX, and HardCopy® IV GX devices with Deterministic Latency mode and enabling the PLL PFD Feedback and using the Byte Serializer are affected when using the Quartus II software versions from 9.1 to 10.0 SP1.
- Cyclone® IV GX devices with Deterministic Latency mode and enabling the PLL PFD Feedback are affected when using the Quartus II software versions 10.0 and 10.0sp1.
Note that the Altera CPRI MegaCore (which does not utilize the PLL PFD Feedback feature) and Arria II GZ devices are not affected by this issue.
This issue is scheduled to be fixed in a future version of the Quartus II software. If this issue is causing an immediate problem, file a Service Request using mySupport.