Article ID: 000078726 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there known issues regarding Cyclone III M9K memory block read corruption when used with clock enables in Quartus II software version 7.1?



Yes, Altera® has identified a read issue when using the M9K memory blocks of Cyclone® III EP3C25 devices in a certain configuration for designs compiled with the Quartus II software version 7.1 and earlier. In this case memory reads may produce incorrect data. At the device level this issue only occurs in True Dual-Port mode, with dual clocks (for Port A and Port B), with dual clock enables, with one clock enable signal connected to VCC in the design, and with a certain register packing. Due to memory packing optimization in the Quartus® II software, memory blocks that appear as any supported memory mode such as Single-Port Mode or ROM Mode may actually utilize the M9K memory block in True Dual-Port Mode.

This issue is caused by incorrect routing of the clock enable signals.

You can avoid this issue if you do not use clock enables on any memory in your design.  For example, if you use the RAM MegaWizard® Plug-In Manager, you must not check the “Create one clock enable for each clock signal” option for any memory in the design.

This issue is fixed beginning with the Quartus II software version 7.1 SP1.

For Quartus II version 7.1, there is a patch available. Please use mySupport to request patch 0.13.

Related Products

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Cyclone® III FPGAs