Article ID: 000078697 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Why are there bit errors when I perform an RTL simulation of an external serial loopback on Stratix V and Arria V transceiver devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see bit errors when performing an RTL simulation of an external serial loopback of Stratix® V and Arria® V transceiver devices due to a Mentor Graphics Modelsim® resolution and rounding issue.

Resolution

To work around this issue, you should set the precision of the simulation to fs.

Related Products

This article applies to 7 products

Stratix® V GX FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA

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