Critical Issue
Description
VHDL simulation fails for the example designs described in the Getting Started with the Arria V Hard IP for PCI Express chapter of the Arria V Hard IP for PCI Express User Guide and for “Getting Started with the Stratix V Hard IP for PCI Express” chapter of the Stratix V Hard IP for PCI Express User Guide.
Resolution
This issue is fixed in version 12.0 of the PCI Express IP cores.