Maximum pending read values in clock crossing bridges for designs migrated from SOPC Builder to Qsys might cause an out of memory error

In a design migrated from SOPC Builder to Qsys, the clock crossing bridge might be parameterized with a large maximum pending reads value. The maximum value causes Qsys to attempt to generate a very deep FIFO buffer in the interconnect, possibly resulting in an out of memory error.

This issue is fixed in the Quartus® II software release version 14.0.

To avoid the creation of a very deep FIFO buffer in previous versions of the Quartus II software, perform the following steps:

1. Instantiate a pipeline bridge that has the same parameterization for address, data width, and maximum burst size before the clock crossing bridge and then disable pipelining. This ensures that no logic is generated between the pipeline bridge and the clock crossing bridge.
2. Set the maximum pending read transactions value of the pipeline bridge to a maximum of 32. This limits the FIFO buffer depth to the specified value.