Description
You may see the above Quartus® II software fitter error when placing a transceiver channel with standard PCS enabled in channels Ch1 and Ch2 of GXB_L0 and GXB_R0 on Arria® V GX, SX, GT, and ST devices. The error occurs when the "Enable rx_pma_clkout port" option is enabled in the Arria V Native PHY IP.
Due to Arria V GX, SX, GT, and ST device limitations, the parallel recovered clock from the CDR and deserializer can not be routed to FPGA fabric.
Resolution
To work around this problem, you must deselect "Enable rx_pma_clkout port" option in the Native PHY IP.
