Article ID: 000078410 Content Type: Product Information & Documentation Last Reviewed: 01/20/2014

How can I check the results of the RAM bit Reservation settings in Cyclone III designs?

Environment

    Quartus® II Subscription Edition
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Description

To check the results of the RAM bit reservation settings in Cyclone® III designs, follow these steps:

1. Locate the RAM in the Resource Property Editor

2. Check the Connectivity View.

For the Input Ports, the disabled bitlines are named in the Signal Name column as 

|<ram instance name>|~QUARTUS_CREATED_GND_I .

For the Output Ports, the disabled bitlines are named in the Signal Name column as 

|<ram instance name>|~QUARTUS_CREATED_GND~I~FITTER_CREATED_DUMMY_SLICE

|<ram instance name>|~QUARTUS_CREATED_GND~I~FITTER_CREATED_DUMMY_SLICE_<n>

Figure 1 Input port

Figure 1

Figure 2 Output port

Figure 2

 

Resolution

 

Related Products

This article applies to 1 products

Cyclone® III FPGAs

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