Article ID: 000078376 Content Type: Troubleshooting Last Reviewed: 10/12/2011

Qsys creates a reset input for every clock source in a system converted from SOPC Builder

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 10.1

FPGA Intellectual Property

Reset

Version Found: 10.1

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

When converting an SOPC Builder system with more than one clock source to Qsys, Qsys creates multiple reset inputs one for each clock source.

Resolution

In the top level of your design, connect all reset inputs generated by Qsys to the same reset source.

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